The present invention generally relates to a jumper for a semiconductor assembly and, in particular, relates to one such jumper having means for relieving stresses created therein during the use thereof.
The provision of electrically conductive jumpers in semiconductor assemblies has usually been constrained to substantially lateral, although possibly somewhat vertically displaced, interconnections. One reason for such a constraint is that in most semiconductor assemblies connections, for example, wire bonds, are formed of conductive material having relatively small cross-sectional areas. Such connections tend to be weakened when sharp bends are required along the length thereof. Further, most bonding machines, particularly those adapted for automated operation, are designed to form bonds in the plane perpendicular to the bonding heads thereof. As a result, to increase the speed of assembly, inter alia, conventional semiconductor assemblies are designed so that the bonding pads lie in substantially the same plane as the points to be connected thereto.
Another basis for such a constraint is, at least for semiconductor assemblies dissipating substantial quantities of power, that one surface of all the semiconductor components of the semiconductor assembly is usually attached to a heat sink. Consequently, the use of non-lateral jumpers between, for example, opposing surfaces of such an assembly has been unwarranted.
One particular vehicle that exhibits these constraints is the so-called wafer scale assembly. In general, a wafer scale assembly is a conglomeration of interconnected semiconductor chip devices and/or subassemblies mounted on one surface of a common substrate. The common substrate can be, for example, a semiconductor material, such as a silicon wafer, and usually includes electrically conductive interconnections formed on the one surface thereof. Typically, wafer scale assemblies allow many chips to be interconnected into a single operative device in a reliable fashion. That is, such a wafer scale assembly is considered more reliable than a fully integrated identical device formed by conventional semiconductor integrated circuit fabrication techniques. One reason for the increased reliability is that the individual chips can be tested prior to affixing them to the wafer scale assembly substrate. Such wafer scale assemblies have numerous advantages in addition to the increased reliability thereof. For example, wafer scale assemblies generally exhibit an excellent thermal matching between the substrate and the chips/subassemblies affixed thereto and consequently, stresses resulting from thermal expansions and contractions are less destructive. Further, wafer scale assemblies offer high chip density circuits and arrangements similar to that of chip size integrated devices. In addition, wafer scale assemblies have a relatively low cost per function as well as the ability to mix different types of integrated circuits, i.e., MOS and BIPOLAR chips, on the same silicon substrate.
Currently, many semiconductor assemblies include a ceramic substrate having a plurality of pins extending perpendicular from a major surface thereof with the assembly mounted to the opposing major surface of the ceramic substrate.
However, in an environment where the surface generating the heat to be dissipated is the surface exposed to the primary coolant it becomes possible to mount pairs of semiconductor assemblies back-to-back. One particular cooling package is described and discussed in U.S. patent application Ser. No. 859,964 filed on even data herewith and entitled PACKAGE FOR A SEMICONDUCTOR ASSEMBLY. A header for such a semiconductor assembly that is designed, inter alia, to enhance the ability to mount, for example, two wafer scale assemblies in back-to-back fashion is described and discussed in U.S. patent application Ser. No. 859,942 filed on even date herewith and entitled HEADER FOR A WAFER SCALE ASSEMBLY. Both of the above referenced applications are assigned to the assignee hereof and incorporated herein by reference.
Consequently, since semiconductor assemblies, such as wafer scale assemblies, can now be practically connected in a back-to-back fashion, it has become highly desireable to provide a jumper that is reliable and particularly adapted for connecting to pluralities of pads on opposing surfaces of such a semiconductor assembly.